The device size becomes smaller and smaller and the chip integration level becomes higher and higher along with continuous development of semiconductor process. By the scaling-down theory, the source voltage VDD of a chip also becomes increasingly lower along with the process. However, a high voltage circuit or a high voltage device still may be used in the chip due to a system demand or a need for improved chip performance. In order to realize integration, usually a charge pump circuit is introduced to boost the source voltage VDD to a high voltage for internal use.
Referring to FIG. 1, a four-stage Dickson charge pump is illustrated, which consists of five NMOS transistors M1, M2, M3, M4 and M5, four charging capacitors C1, C2, C3 and C4, and a storage capacitor Cf. The gate of each NMOS transistor is coupled with its drain, the output terminal of each NMOS transistor is coupled with one terminal of a charging capacitor and the input terminal of the next NMOS transistor, the input terminal of the first NMOS transistor M1 is coupled with the input voltage VDD, and the output terminal of the last NMOS transistor is coupled with the storage capacitor Cf. The other terminal of an odd stage of charging capacitor is coupled with a first clock signal CLK, and the other terminal of an even stage of charging capacitor is coupled with a second clock signal CLKB. The other terminal of the storage capacitor Cf is grounded.
Referring to FIG. 2, FIG. 2 illustrates a diagram of the first clock signal CLK and the second clock signal CLKB varying with time, where the first clock signal CLK and the second clock signal CLKB provide voltage signals with a square wave shape and with a magnitude between 0 and the VDD, and the first clock signal CLK and the second clock signal CLKB are anti-phase clocks signals. When the first clock signal CLK is at the VDD, the second signal CLKB is at 0V, and when the first clock signal CLK is at 0V, the second signal CLKB is at the VDD.
Referring to FIG. 1, an initial voltage on capacitor C1 is 0 when the first clock signal CLK is at 0V. At this time, the transistor M1 is turned on, and thus the charging capacitor C1 is charged with the input voltage VDD until the voltage on capacitor C1 is at the VDD. When the first clock signal CLK is at the VDD, the voltage of the other terminal of the charging capacitor C1 is boosted to two times the VDD because the voltage on capacitor C1 is kept stable. Similarly, the voltage can be boosted with the VDD each time it passes through a charge pump including a NMOS transistor and a charging capacitor. Finally, the output voltage Vout with an increase of four times the VDD relative to the input voltage is provided stably through the storage capacitor Cf.
In the above circuit, each NMOS transistor with the gate and the source in connection may give rise to a loss of threshold voltage, and this may reduce the voltage gain of the charge pump circuit, lower transmission efficiency of the charge pump circuit and further increase area of the circuit. Also each stage of transmission unit may be insufficiently turned on along with the steadily lowered VDD, thereby influencing the efficiency of boosting the voltage through the charge pump.
Furthermore, the threshold voltage is also related to the substrate source voltage, and since the output voltage of each NMOS transistor differs from those of several preceding transistors, the threshold voltage of each transmission unit also differs. Even if the minimum gate-source voltage required for turning on each NMOS transistor differs and although several preceding NMOS transistors can be turned on thoroughly, the turn-on of the NMOS transistors may become more and more insufficient and seriously even an NMOS transistor in a transmission unit may fail to be turned on along with the increment of the numbers of transistors, thereby influencing normal work of the entire circuit.
Another modified Dickson charge pump circuit is disclosed in the prior art. As illustrated in FIG. 3, the charge pump consists of (m+1) stages of transmission units (where m≧1), m stages of charging units and an energy storage unit Cf.
Taking the first stages of transmission unit as an example, the first stage of transmission unit includes three PMOS transistors QT1, QS1 and QD1, where the gate and the drain of the first PMOS transistor QT1 are coupled with the gate of the second PMOS transistor QS1 and the drain of the third PMOS transistor QD1; the source of the first PMOS transistor QT1 is coupled with the source of the second PMOS transistor QS1 and the gate of the third PMOS transistor QD1; the substrate of the first PMOS transistor QT1 is coupled with the substrate and the drain of the second PMOS transistor QS1 and the substrate and the source of the third PMOS transistor QD1.
Except for the first and the last stages of transmission units, the gate and the drain of the first PMOS transistor in any other stage of transmission unit act as the output of the transmission unit, which is coupled with one terminal of a charging unit and the source of the first PMOS transistor in the next stage of transmission unit; the source of the first PMOS transistor QT1 in the first stage of transmission unit is coupled with an input voltage VDD; and the gate and the drain of the first PMOS transistor in the last stage of transmission unit act as the output of the last stage of transmission unit, which is coupled with one terminal of the energy storage unit Cf The charging unit and the energy storage unit Cf consist of capacitors. The other terminal of the odd stage of charging unit is coupled with the first clock signal CLK, and the other terminal of the even stage of charging unit is coupled with the second clock signal CLKB.
In this modified Dickson charge pump circuit, the substrate source voltage is made substantially stable by coupling two bias PMOS transistors at the substrate, thereby avoiding the occurrence of a phenomenon that an MOS transistor fail to be turned on due to a too large threshold voltage. However, this structure can not ensure sufficient turn-on of the PMOS transistors in all the transmission units in the case of a low input voltage VDD and may be inefficient with boosting the voltage at each stage. The inefficiency of transferring may require a circuit with a larger number of stages, thereby resulting in a slowed processing speed, more noise and an increased chip area of the circuit.